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| BCD DECADE/MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS The SN54 / 74LS168 and SN54 / 74LS169 are fully synchronous 4-stage up/down counters featuring a preset capability for programmable operation, carry lookahead for easy cascading and a U / D input to control the direction of counting. The SN54 / 74LS168 counts in a BCD decade (8, 4, 2, 1) sequence, while the SN54 / 74LS169 operates in a Modulo 16 binary sequence. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. SN54/74LS168 SN54/74LS169 BCD DECADE / MODULO 16 BINARY SYNCHRONOUS BI-DIRECTIONAL COUNTERS LOW POWER SCHOTTKY * * * * * * * Low Power Dissipation 100 mW Typical High-Speed Count Frequency 30 MHz Typical Fully Synchronous Operation Full Carry Lookahead for Easy Cascading Single Up / Down Control Input Positive Edge-Trigger Operation Input Clamp Diodes Limit High-Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 16 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET 10 PE 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 1 U/D 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP GND ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. CEP CET CP PE U/D P0-P3 Q0-Q3 TC Count Enable Parallel (Active LOW) Input Count Enable Trickle (Active LOW) Input Clock Pulse (Active positive going edge) Input Parallel Enable (Active LOW) Input Up-Down Count Control Input Parallel Data Inputs Flip-Flop Outputs Terminal Count (Active LOW) Output 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOGIC SYMBOL 9 3 4 5 6 NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. 1 7 10 2 PE P0 P1 P2 P3 U/D CEP TC CET CP Q0 Q1 Q2 Q3 15 14 13 12 11 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 SN54/74LS168 * SN54/74LS169 STATE DIAGRAMS SN54/ 74LS168 UP / DOWN DECADE COUNTER 0 1 2 3 4 0 SN54 / 74LS169 1 2 3 4 15 5 Count Up Count Down 15 5 14 6 14 6 13 7 13 7 12 11 10 9 8 12 11 10 9 8 SN54 / 74LS168 UP: TC = Q0 Q3 (U / D) DOWN: TC = Q0 Q1 Q2 Q3 (U / D) SN54 / 74LS169 UP: TC = Q0 Q1 Q2 Q3 (U / D) DOWN: TC = Q0 Q1 Q2 Q3 (U / D) LOGIC DIAGRAMS SN54 / 74LS168 P0 PE P1 P2 P3 CEP CET U/D TC CP CP D Q0 Q1 Q2 Q3 FAST AND LS TTL DATA 5-2 SN54/74LS168 * SN54/74LS169 LOGIC DIAGRAMS (continued) SN54 / 74LS169 P0 PE P1 P2 P3 CEP CET U/D TC CP CP D Q0 Q1 Q2 Q3 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA FAST AND LS TTL DATA 5-3 SN54/74LS168 * SN54/74LS169 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current Other Inputs CET Input Other Input CET Input IIL IOS ICC Input LOW Current Other Input CET Input Short Circuit Current (Note 1) Power Supply Current - 20 0.35 0.5 20 40 0.1 0.2 - 0.4 - 0.8 - 100 34 V A 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIH mA VCC = MAX, VIN = 7.0 V mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at one time, nor for more than 1 second. FUNCTIONAL DESCRIPTION The SN54/74LS168 and SN54/74LS169 use edgetriggered D-type flip-flops that have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a set-up time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the P0 - P3 inputs enters the flip-flops on the next rising edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH. The U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the COUNT DOWN mode or reaches 15 (9 for the SN54/74LS168) in the COUNT UP mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. The TC output of the SN54/74LS168 decade counter can also be LOW in the illegal states 11, 13 and 15, which can occur when power is turned on or via parallel loading. If illegal state occurs, the SN54/74LS168 will return to the legitimate sequence within two counts. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended. MODE SELECT TABLE PE L H H H H CEP X L L H X CET X L L X H U/D X H L X X Action on Rising Clock Edge Load (Pn Qn) Count Up (increment) Count Down (decrement) No Change (Hold) No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial FAST AND LS TTL DATA 5-4 SN54/74LS168 * SN54/74LS169 AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter P Maximum Clock Frequency Propagation Delay, Clock to TC Propagation Delay, Clock to any Q Propagation Delay, CET to TC Propagation Delay, U / D to TC Min 25 Typ 32 23 23 13 15 15 15 17 19 35 35 20 23 20 20 25 29 Max Unit Ui MHz ns ns ns ns VCC = 5.0 V 50 CL = 15 pF Test C di i T Conditions AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol S bl tW ts ts ts th Parameter P Clock Pulse Width Setup Time, Data or Enable Setup Time PE Setup Time U/D Hold Time Any Input Min 25 20 25 30 0 Typ Max Unit Ui ns ns ns ns ns Test C di i T Conditions VCC = 5.0 V 50 FAST AND LS TTL DATA 5-5 SN54/74LS168 * SN54/74LS169 AC WAVEFORMS 1/fmax CP 1.3 V tPHL 1.3 V 1.3 V tW tPLH 1.3 V 1.3 V CET 1.3 V tPLH 1.3 V tPHL 1.3 V TC 1.3 V Q OR TC Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width Figure 2. Count Enable Trickle Input To Terminal Count Output Delays CP ts(H) CP 1.3 V tPLH TC 1.3 V 1.3 V 1.3 V tPHL 1.3 V Q0 * Q1 * Q2 * Q3 P0 * P1 * P2 * P3 1.3 V 1.3 V th(H) = 0 1.3 V ts(L) 1.3 V 1.3 V th(L) = 0 1.3 V Figure 3. Clock to Terminal Delays Figure 4. Setup Time (ts) and Hold (th) for Parallel Data Inputs CP ts(L) SR OR PE 1.3 V 1.3 V th(L) = 0 1.3 V ts(H) 1.3 V 1.3 V th(H) = 0 1.3 V U/D tPLH 1.3 V 1.3 V tPHL 1.3 V 1.3 V CP ts(H) CEP 1.3 V ts(H) CET 1.3 V 1.3 V th(H) = 0 1.3 V th(H) = 0 1.3 V ts(L) 1.3 V 1.3 V th(L) = 0 1.3 V ts(L) 1.3 V 1.3 V TC Figure 6. Up-Down Input to Terminal Count Output Delays th(L) = 0 1.3 V The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 5. Setup Time and Hold Time for Count Enable and Parallel Enable Inputs, and Up-Down Control Inputs FAST AND LS TTL DATA 5-6 |
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